RF IC Layout Engineer
We are offering a senior layout engineer position enabling you to join the creation of the next generation mobile phone chips.
The Analog & RF IC Layout Engineer will be part of an experienced layout team. In close cooperation with his colleagues he will be in charge of the layout of high speed analog and RF circuits and he will take up a leading role in the floorplanning and optimization of the system on chip.
He is an expert user of Cadence and Mentor tool suites on nanometer RF CMOS and/or RF SOI technology.
The successful candidate will work closely with the RF designers. He/she will take into account the constraints from the designer and will go through iterations with the designer to further optimize the layout from a performance and area perspective.
RF circuit layout experience in the sub 10-Ghz range is mandatory.
The layout engineer should have a good understanding of the different circuit topologies and their constraints for the layout. implementation. Good understanding of the layout rules enable to optimize the implementation.
The senior layout engineer is also capable of performing extraction and making the interpretation of these results in view of further optimization.
Industry Degree qualified (BS or MS EE degree)
Ample experience with the Cadence OA VirtuosoXL
Experience with RFIC layout (GHz range) in CMOS technology
Finfet experience is a major plus.
Automation for layout is a plus.
Good communication skills and team-player.
Process oriented, ability to structure the RF layout process
Continuous strive for improvement in circuits and processes.
Detail oriented and determined
Relocation to Belgium, if applicable, is strongly recommended.