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Ultra low power SRAM design in finFET CMOS technology

Ultra low power SRAM design in finFET CMOS technology

The MICAS group of the Department of Electrical Engineering (ESAT) of the KU Leuven is a world-class research group in the domain of analog, digital and mixed signal integrated circuit design. Within the MICAS group the team of Professor Wim Dehaene, focusses on circuit level digital design. Designs are addressed at RT-Level but we do not avoid the circuit level: libraries are optimized, new circuit topologies are allowed. In this way we investigate and realize ultra low energy circuits for IoT for example.

In the project, the researcher will analyze the problem on a theoretical level based on literature and own analysis. In addition, practical demonstration of the findings will be part of the work. One or more demonstrato rchips will be built in finFET technology. You will also measure your circuits. The silicon chips are the ultimate proof of the novel circuit concepts that are invented. The SRAM memories will be manually designed at circuit level. Automatic layout generation will be used whenever possible but this is not the focus of the proposed research.

* You have a master in electrical engineering
* Circuit design at RT, gate and physical level is part of your skill set
* You have good programming skills.
* You have a good written and spoken knowledge of the English language
* You are an enthusiastic young researcher willing to work in a team but also capable of developing your own knowledge.

We offer a PhD research position at KU Leuven ESAT-MICAS, a young, dynamic top-notch research environment. The position is coupled to a KU Leuven scholarship and is rewarded accordingly. After successful completion of the research in 4 to 5 years, you will acquire a PhD title from KU Leuven. Depending on your antecedents you will have to pass a predoctoral examination.

Leuven

KU Leuven - Universiteit

Ultra low power SRAM design in finFET CMOS technology

KU Leuven, Leuven
Categories: 
Technical Consultant, Design Engineer
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